Moore's Law Delay: Intel Postpones Next-Gen Chips

Intel revealed during its second-quarter earnings call Wednesday that it would delay the release of its Cannonlake chips manufactured on the 10-nanometer process to the second half of 2017. The chips had been slated for launch in 2016.

The news marks a crack in Intel's scheduling system of shrinking its transistors every two years, dubbed "Moore's Law," as chips become more intricate and complex to build.

"On all of these technologies, each one has its own recipe of complexity and difficulty, and 14-nanometer to 10-nanometer [is the] same thing that happened from 22-nanometer to 14-nanometer," said Intel CEO Brian Krzanich on the call. "The lithography is continuing to get more difficult as you try and scale, and the number of multipattern steps you have to do is increasing."

[Related: Report: Intel May Hold On To 10nm Cannonlake Microarchitecture Platform]

Intel's upcoming sixth-generation microarchitecture, Skylake, the successor to the current Broadwell platform, will baptize a slew of 14-nanometer processors and is expected to be released at the Intel Developer Forum on Aug. 15.

The platform scheduled to be released after that, the 10-nanometer Cannonlake microarchitecture, represents a "tock" in Intel's "tick-tock" staggered release schedule based on Moore's Law; while the "tick" symbolizes a reproduction in node size, "tock" represents a new architecture.

However, Intel will delay the Cannonlake microarchitecture and fill the gap with a new microarchitecture that is a 14-nanometer derivative of Skylake, dubbed Kaby Lake, representing a third generation of optimized processors. Little has been revealed about the Kaby Lake lineup.

Though Intel has been utilizing its "tick-tock" schedule since 2007, delays occurred last year as the Santa Clara, Calif.-based company's 14-nanometer Broadwell chips were pushed behind schedule, as chips become smaller and more difficult to manufacture in a hyper-competitive semiconductor industry.

Jim McGregor, founder and principal analyst at research firm Tirias Research, said that while companies have been making innovations in transistor designs and materials for chips, completing the lithography process as chips continually grow smaller has been a tough battle for chip giants such as Intel.

"Intel wants to upgrade its architecture on that tick-tock model, but it's getting more challenging to maintain Moore's Law as lithography has been a huge problem," said McGregor. "This is the first time we're seeing sub-node steps with Kaby Lake. … Intel's going to have to start optimizing other process nodes and taking smaller steps in technology evolution, which is what most other companies do."

Intel disclosed its situation a week after IBM revealed it is developing a 7-nanometer chip in conjunction with GlobalFoundries, Samsung and SUNY Polytechnic Institute's Colleges of Nanoscale Science and Engineering. However, stressed McGregor, while IBM is a competitive threat to Intel, the advancement of the 7-nanometer chip is still far off and has to deal with lithography challenges as well.

Douglas Grosfield, president and CEO of Xylotek Solutions, a Cambridge, Ontario-based Intel partner, said the innovations stemming from the competition between these companies will ultimately benefit partners of both Intel and IBM.

"Silicon is rapidly nearing the end of its capacity for these increases in chip density, and new or hybrid materials are necessary to achieve the increases necessary to keep pace with historical accomplishments," said Grosfield. "IBM is doing cool things with silicon derivatives, so we will see all chip manufacturers investing heavily in [research and development] as usual, to build a better mousetrap. As a partner to both Intel and IBM, Xylotek is excited to see the developments over the next couple of years."

PUBLISHED JULY 16, 2015